The present invention relates to a novel method and system for analyzing semiconductor bitmap test data.
Integrated circuits (ICs) are commonly manufactured through a series of processing steps. Very often more than a hundred processing steps are performed to produce a properly functioning integrated circuit chip.
A semiconductor material, commonly in the shape of a wafer, serves as the substrate for integrated circuits. Semiconductor ICs are typically manufactured as an assembly of a hundred or more chips on a single semiconductor wafer which is then cut up to produce the individual IC chips. Typically, a wafer made of silicon is used as the integrated circuit substrate, the silicon wafer being approximately 150-300 mm in diameter and 0.6-1 mm thick. During the manufacturing process, the silicon wafer is first polished and cleaned to remove all contaminant particles situated thereon. The silicon wafer is then treated in preparation for a series of processing steps involving a plurality of photolithographic patterns (also commonly referred to as masks). In the production of integrated circuits, microelectronic circuits are formed onto the silicon wafer through a process of layering. In the layering process, conductive and insulative layers of thin films are deposited and patterned onto the silicon wafer. Each layer is patterned by a mask designed specifically for it, the mask defining the areas within the wafer that are to be treated such as by etching or implanting.
Semiconductor fabrication technology today deals with silicon wafers which are approximately 200 mm in diameter and which feature geometries with dimensions well below 0.5 μm (micrometer). Due to the high complexity and level of integration of integrated circuits, the absence of processed induced defects on every layer of the wafer is critical in order to realize acceptable levels of product yield. Specifically, the presence of one processed induced defect larger than the half the width of a conductive line on the silicon wafer can result in the complete failure of a semiconductor chip produced from the wafer. Such a chip has to be discarded which thereby decreases the percentage yield per wafer and increases the overall cost of the individual wafers. Therefore, a critical task facing semiconductor process engineers is to identify and, as soon as possible, to eliminate sources of processed induced defects on each layer of a semiconductor wafer.
Accordingly, memory devices (e.g., DRAM, SRAM and FLASH memory devices) and logic devices which include integrated circuits manufactured from a semiconductor wafer require production monitoring and testing. The results generated from semiconductor wafer monitoring and testing are then used during a failure analysis process to more accurately treat problems introduced into the integrated circuits, as will be discussed further below.
Memory chips, because of their structure as coordinated arrays of memory cells, readily lend themselves to failure analysis. As a result, each integrated circuit formed on a semiconductor wafer is tested before the integrated circuit is packaged as a memory device. Specifically, electrical probes connected to a test station contact pads on the integrated circuit to monitor the functionality of the individual cells of a memory device.
As an example, a memory device can be tested by disposing the electrical probes into contact with address pads on the integrated circuit in order to access selected memory cells for the memory device. A predetermined set or pattern of test data is written into selected addresses that correspond to certain memory cells in the memory device. The test data is then read from those memory cells to determine if the test data, as read, matches the test data, as written. If the test data, as read, does not match the test data, as written, a semiconductor failure analysis engineer often deduces that the particular memory cells corresponding to the selected addresses are faulty.
Automatic test equipment (often referred to simply as ATE or testers in the art) are well known and are widely used to test individual memory cells of a memory device. The test data generated by automatic test equipment, in turn, can be used to identify the physical addresses (i.e., the row and column) of the faulty memory cells of a memory device. The individual memory cells, or bits, of a memory device are then often mapped into a bitmap display to assist in the identification of the faulty cells.
A bitmap display is a representation which provides the functional test results of each memory cell of a memory device and, in turn, provides a physical location array. Specifically, a bitmap display generates the test data accumulated by the automatic test equipment for a memory device as a matrix of square boxes. Each box represents an individual memory cell, the boxes often being arranged in direct relation to the physical location of the memory cells on the die. Each box of the matrix is often assigned a numerical value or color based on the performance of its corresponding cell during the testing process. For example, a properly functioning cell is often represented as a white box and a faulty cell is often represented as a black box.
Using a bitmap display, a semiconductor failure analysis engineer often examines faulty memory cells using a high intensity microscope to determine the reason for the errors (e.g., whether the errors occurred from masking defects, during deposition of certain layers, etc.). However, due to the large quantity of faulty memory cells which can be present on a single integrated circuit, individually examining each faulty memory cell under a high intensity microscope is often deemed too time-consuming.
Accordingly, the faulty cells of a bitmap display are often grouped into certain fundamental, or base, failure patterns (e.g., a block pattern failure, a column failure or a row failure). Failure patterns (also referred to herein as fault shapes) enable a failure analysis engineer to cluster together multiple faulty cells for further analysis, thereby reducing the overall amount of time required to examine the faulty cells of a memory device, which is highly desirable.
It should be noted that the particular shape of a failure pattern can often enable a failure analysis engineer to identify the root cause of the failure and/or estimate where in the production process the failure was introduced, which is highly desirable. Having identified where in the production process the failure occurred, the failure analysis engineer can attempt to clean up the manufacturing process to prevent further failures. In addition, the failed memory cells may be repaired by re-mapping the failed memory cells to redundant cells in the die.
Conventional methods for identifying fault shapes in bitmap displays apply a failure pattern mask at every position of the bitmap matrix in the spacial domain in order to locate particular failure patterns. The process of matching the pattern mask onto the bitmap display is typically accomplished through a bit by bit match of the pattern mask onto the bitmap matrix. The existence of a direct match signifies the identification of the pattern mask in the bitmap display at said location in the bitmap matrix. The identified failure pattern is then saved for future analysis by an engineer.
Although well known and widely used in the art, the conventional method of identifying fault shapes in bitmap displays by performing a bit by bit match of the pattern mask at every position of the bitmap matrix in the spatial domain suffers from a notable drawback. Specifically, the process of performing a bit by bit match of the two matrixes in the spatial domain requires the implementation of algorithms which are highly complex in nature. As a result, the process of performing the bit by bit match of the pattern mask in the spatial domain and the bitmap matrix in the spatial domain significantly slows down the entire analysis process, which is highly undesirable. In fact, the bitmaps generated for a single semiconductor wafer can require up to 24 hours to analyze using conventional analyzation methods, which is highly undesirable.